Introduction

This paper describes the design and implementation of an address sequencer that controls the sequence of execution of microinstructions stored in microprogram memory. In addition to the capability of sequential access, it provides conditional branching to any microinstruction within its 4096-microword range. A last-in, first-out stack provides microsubroutine return linkage and looping capability; there are eight levels of nesting of microsubroutines. (Unknown, p.1)

This Basic Microinstruction Sequencer (BMS) is modelled after the AM29C10A chip. Only a modified subset of the instructions of the AM29C10A was implemented to ensure that the BMS design conforms to the tiny chip form factor necessary to ensure that the BMS can be built by MOSIS.

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Last updated 11/21/96.