Instruction ROM

Design Overview

The Basic Microinstruction sequencer (BMS) is designed to handle 8 different microinstructions. The Instruction ROM basically acts are the instruction coder and control logic for the operation of the BMS. 4 control signals are generated by the ROM based on an input of 3 bits of instruction code and 2 bits of condition code. The instruction set supported by the ROM is shown in the table below.

A ROM was used instead of a PLA for ECO-tolerance, since there wasn't a tight constraint on area. In the event that changed to the opcodes have to be made, it would be much simpler to modify a ROM rather than a PLA. The ROM consists of three main components: a 3-to-8 decoder, a 8-to-1 selector and a pulldown array.

Instruction Set


I2-I0	MNEMONIC	NAME	FAIL /CCEN=L and /CC=H Y / STACK	PASS /CCEN=H or /CC=L Y / STACK
0	JZ	JUMP ZERO	0 / CLEAR	0 / CLEAR
1	CJS	COND JSB	PC / HOLD	D / PUSH
2	CJP	COND JUMP	PC / HOLD	D / HOLD
3	CPUSH	COND PUSH	PC / HOLD	PC / PUSH
4	CPOP	COND POP	PC / HOLD	PC / POP
5	CRTN	COND RTN	PC / HOLD	F / POP
6	CJPP	COND JUMP & POP	PC / HOLD	D / POP
7	CONT	CONTINUE	PC / HOLD	PC / HOLD

Design Schematics

The following are the schematics for the design:

Decoder

The decoder is basically made up of 8 3-input AND gates each supplied with an appropriate version of the 3 input signals.

[Decoder Schematic]

The transistor-level schematics for the individual components are available: inverter and 3-input AND-gate.

Selector

The selector is simply a chain of 4 2-input muxes driven by an inverter.

[Selector Schematic]

The transistor-level schematics for the individual components are available: inverter and 2-input multiplexor.

Instruction ROM

The Instruction ROM was constructed from the decoder and selector described above with a pulldown array. The coding scheme for the 4 output signals are given in the following section.

[ROM Schematic]

The schematics for the decoder and the selector are shown above, other transistor-level schematics for lower-level individual components are available: inverter, 2-input NAND-gate with one inverted input, pullup and pulldown.

Output Encoding

S1	S0	Instruction to Stack
0	0	Clear
0	1	Hold
1	0	Push
1	1	Pop

M1 M0 Instruction to Multiplexor

0 0 Zero

0 1 Program Counter

1 0 External Data

1 1 Stack Input

Comments to benleong@mit.edu or mike_sy@mit.edu or sclee@mit.edu
Last updated 11/21/96.

M1	M0	Instruction to Multiplexor
0	0	Zero
0	1	Program Counter
1	0	External Data
1	1	Stack Input