Titlepage | Introduction | Overview | ROM | Datapath | Layout | Conclusion | References.

Testing

Overview

This is a rather large project. As a result, we exploit the hierarchical structure of the design and conduct our testing procedures at different levels. Firstly, individual modules are tested at the schematic level with both Lsim and Hspice. Since the interfaces between the different modules are well-defined, it is rather straightforward to generate test cases to check if input/output constraints are satisfied. Next, when it was found that individual components were working correctly, all the schematics are combined into a schematic version of the sequencer. A microprogram was written and encoded into a schematic ROM cell. The resulting Microcontroller Unit schematic was simulated in Hspice to ensure that all components are interacting correctly.

Once the schematic-level simulations were found to be successful, layouts for the individual cells were done and they were simulated and tested with the tests developed for the schematics in order to ensure correctness. Finally, the layouts for the individual modules were integrated and tested as a system.

Details:

• Schematic-level Component Testing
• Schematic-level Integrated Testing
• Layout-level Component Testing
• Final Integrated Testing

Comments to benleong@mit.edu or mike_sy@mit.edu or sclee@mit.edu
Last updated 11/21/96.

Titlepage | Introduction | Overview | ROM | Datapath | Layout | Conclusion | References.