Final Testing of Integrated System

Overview

The final testing of the integrated system was done using the layout version of the sequencer. The setup is exactly the same as in the schematic case. See Schematic-Level Testing of Integrated System for reference. Basically, Led is used to convert the layout into a schematic and the resulting schematic is used as before for the simulation.

Results

The results for the testing of the layout is shown below:

[Integrated Simulation Timing Diagram 1]

[Integrated Simulation Timing Diagram 2]

[Integrated Simulation Timing Diagram 3]

[Integrated Simulation Timing Diagram 4]

[Integrated Simulation Timing Diagram 5]

Overall, the system seems to be working correctly except for the fact that FULL is not assert even though it should have been asserted at various points. We plan to fix this problem before we fabricate the chip.

System Timing

The following plot was produced by Lsim executing the same program used for schematic-level timing

[System Layout Timing]

The plot shows that the worst delay through the chip occurs when it is executing a pop instruction. However, this delay does not at all reflect the true delay of the chip, as pop data is available only on the low part of the clock cycle. Given that the next slowest delay is 31ns when all the carries of the current location propagate, we estimate that the chip should be able to handle a clock rate of 25Mhz. Unfortunately we were not able to test the chip at this rate because we ran out of time. Note that again this simulation does not account for the delay of the external program ROM and the delay of the inputs and outputs through the pads of the chip. The chip can be expected to run at approximately 10Mhz taking these factors and the layout simulation into account.

Comments to benleong@mit.edu or mike_sy@mit.edu or sclee@mit.edu
Last updated 11/21/96.