Layout Testing

Instruction ROM

The ROM layout test results are shown below.

[ROM Test Results]

Stack

The layout of the stack and the stack pointer were tested together with the results shown below.

[Stack Test Results]

Datapath

Program Counter

Incrementer

The following plot was generated using the layout of the program counter incrementer using Lsim in adept mode with a Simulation Interval of 0.1 ns. The worst unloaded propagation delay across the incrementer was found to be approximately 21ns which is slightly worse than the 17ns delay result from the schematic simulation .

[Incrementer Test Results]

Register

The following plot was generated using the layout of the program counter register using Lsim in adept mode with a Simulation Interval of 0.1 ns. The worst unloaded propagation delay across the register was found to be approximately 3ns which is about the same as the 3ns delay result from the schematic simulation .

[Register Test Results]

Multiplexor

The following plot was generated using the layout of the program sequencer multiplexor using Lsim in adept mode with a Simulation Interval of 0.1 ns. The worst unloaded propagation delay across the MUX was found to be approximately 3ns which is surprisingly faster than the 3ns delay result from the schematic simulation .

[Multiplexor Test Results]

Comments to benleong@mit.edu or mike_sy@mit.edu or sclee@mit.edu
Last updated 11/21/96.