Design and Implementation of Main Datapath

Overview

The main datapath consists of the sequencer's MUX, program counter, and stack.

Stack Memory

The stack memory is connected to the datapath, getting some of its inputs from the PC register and providing inputs to the output mux. It also takes in inputs from the ROM to indicate a write operation and a 3-bit address input from the stack pointer.

It was implemented using an 8x12-bit SRAM memory module, a clock coupled decoder, a write signal generator and a 12 bit negative edge register. A diagram showing the interconnections are shown Figure 1.

[Block Diagram for the Stack]

Figure 1. Block Diagram for the Stack

The 8x12-bit SRAM module was designed using the 6-T RAM cell design and a differential sense amplifier shown in Figures 2 and 3. The 8 word deep stack was achieved by stacking up the 6-T RAM cell and attaching the sense amplifier, write transistors, write data drivers and the pull up transistors as shown in Figure 4. The 12 bit wide word, on the other hand, was achieved by taking 12 one bit slices of the 8 deep RAM cell and placing them side by side.

[6T RAM Cell]

Figure 2. 6T RAM Cell

[Differetial Sense Amp]

Figure 3. Differential Sense Amp

[1 bit slice of the Stack]

Figure 4. 1 bit slice of the Stack

The clock coupled decoder shown in Figure 5 assures that the word line is only valid to the low edge of the clock cycle when the read and write opreation occurs. This is done to let the bit and bitinv line precharge to vdd on the high part of the clock, thus aiding the read operation.

[Stack Decoder]

Figure 5. Clock Coupled Decoder

The write signal generator was implemented by NOR'ing S1inv and S0, and then AND'ing it to a buffered and inverted clock. The clock needed to be buffered so as to assure that the word line signal from the clock coupled decoder will turn off first before the write signal turns off. This is to assure that the data gets written to the 6-T RAM cell properly.

The 12 bit register at the end is to assure that the write data will be valid until the write is done. This is because of the buffering and inverting of the clock which results in the word lines and the write signal being valid a little after the positive clock edge.

Program Counter

The program counter consists of an incrementer and a register. The location of the current instruction is fed into the incrementer, and the register makes the output of the incrementer available to the MUX at the next clock cycle. If the next instruction calls for sequential execution, then the MUX will select the output of the register as the output of the sequencer.

Incrementer

The incrementer is a cascade of 12 1-bit ripple carry counters.

[Twelve-bit Incrementor]

1-bit counter

Unlike a full adder which essentially adds 3 bits, the incrementer only needs to add 2 bits. Thus, each counter consists of two inputs (in, cin) and two outputs (out, cout), and requires only 2 gates:
cout = AND(in, cin)
out = XOR(in, cin)

[One-bit Incrementor]

Register

The register is a collection of 12 1-bit registers.

[Twelve-bit Register]

1-bit register

Each register consists of a negative master latch and a positive slave latch.

[One-bit Register]

1-bit latch

Each latch consists of a chain of transisters that select between either a feedback path or the input based on the status of the clock signal. The inverter in the circuit makes this latch a static latch.

[One-bit Latch]

Clock driver

Both latches in a 1-bit register are driven by a clock driver that supplies both clock and not clock to the latches.

[Clock Driver]

Multiplexor

The multiplexor (MUX) in the sequencer chooses one of four possible 12-bit addresses for the next instruction. Hence it is a collection of 12 MUXes that select one of four possible 1 bit values. A pair of inverters buffer the select signal from the control ROM.

[Twelve-bit MUX]

Select-from-4 1-bit MUX

Each select-from-4 unit MUX is implmented as a cascade of select-from-1 unit MUXes. The first of two select bits for the select-from-four MUX chooses the output of the first stage of select-from-1 MUXes, while the 2nd select bit chooses one of the outputs of the first stage.

[Select-from-4 1-bit MUX]

Select-from-1 1-bit MUX

The select-from-1 unit MUX is implemented with 2 passgates. The single select bit turns on one of the two passgates.

[Select-from-1 1-bit MUX]

Layout Schematic

[Datapath Overview]

Comments to benleong@mit.edu or mike_sy@mit.edu or sclee@mit.edu
Last updated 11/21/96.