Schematic-level Testing

Instruction ROM

The following plot was generated using the schematic of the Instruction ROM using Lsim in adept mode with a Simulation Interval of 0.1 ns. The propagation delay across the ROM was found to be approximately 5 ns.

[ROM Test Results]

Stack

Ths stack and the stack pointer were tested together and the results attached below show its operation.

[Stack Test Result 1]

[Stack Test Result 2]

Datapath

Program Counter

Incrementer

The following plots were generated using the schematic of the program counter incrementer using Lsim in adept mode with a Simulation Interval of 0.1 ns. The worst unloaded propagation delay across the incrementer was found to be approximately 17ns.

[Incrementer Test Result 1]

Register

The following plot was generated using the schematic of the program counter register using Lsim in adept mode with a Simulation Interval of 0.1 ns. The worst unloaded propagation delay across the register was found to be approximately 3ns.

[Register Test Result 1]

Multiplexor

The following plot was generated using the schematic of the program sequencer multiplexor using Lsim in adept mode with a Simulation Interval of 0.1 ns. The worst unloaded propagation delay across the MUX was found to be approximately 10ns.

[Multiplexor Test Result 1]

Comments to benleong@mit.edu or mike_sy@mit.edu or sclee@mit.edu
Last updated 11/21/96.